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INTEGRATED CIRCUITS
DATA SHEET
TDA1315H Digital audio input/output circuit (DAIO)
Product specification Supersedes data of December 1994 File under Integrated Circuits, IC01 1995 Jul 17
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
FEATURES * Transceiver for SPDIF and "IEC 958" encoded signals * High sensitivity input for transformer-coupled links * TTL-level input for optical links * Built-in IEC input selector * Built-in IEC feed-through function * Automatic sample frequency (fs) detection * System clock recovery from IEC input signal * Low system clock drift when IEC input signal is removed * Error detection and concealment * PLL lock detection in transmit mode * Serial audio interface conforms to I2S-bus format * Auxiliary I2S-bus input for Analog-to-Digital Converter (ADC) * Audio output selector * Microcontroller-controlled and stand-alone mode * 128-byte buffer for user data * Bytewise exchange of user data with microcontroller * Decoding of Compact Disc (CD) subcode Q-channel data * Support for serial copy management system (SCMS) * Light Emitting Diode (LED) drive capability (sample frequency and error indication) * Pin-selectable device address for microcontroller interface * Power-down mode. ORDERING INFORMATION TYPE NUMBER TDA1315H PACKAGE NAME QFP44 PIN POSITION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm GENERAL DESCRIPTION
TDA1315H
The Digital Audio Input/Output circuit (DAIO) of the TDA1315H is a complete transceiver for biphase-mark encoded digital audio signals that conform to the SPDIF and "IEC 958" interface standards (consumer mode), made in the full CMOS-process C200. In the receive mode, the device adjusts automatically to one of the three standardized sample frequencies (32, 44.1 or 48 kHz), decodes the input signal and separates audio and control data. A clock signal of either 256 or 384 times the sample frequency is generated to serve as a master clock signal in digital audio systems. In the transmit mode, the device multiplexes the audio control and user data and encodes it for subsequent transmission via a cable or optical link.
VERSION SOT307-2
1995 Jul 17
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
QUICK REFERENCE DATA All inputs are TTL compatible; all outputs are CMOS compatible; unless otherwise specified. SYMBOL Supply VDD IDDAq IDDDq IDDA IDDD Power Ptot Temperature Tamb Vi(p-p) Control part CHMODE, UNLOCK, FS32, FS44, FS48 AND COPY (OPEN-DRAIN OUTPUTS) VOL VtHL VtLH Vhys Vref RCint (PIN 44) ICHfr ICHph charge-pump output current charge-pump output current frequency detector loop phase detector loop - - 12 24 LOW level output voltage IOL = 3 mA VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V - 0.6 - - - - - - 0.7 operating ambient temperature -20 - - total power dissipation fs = 48 kHz; CLKSEL = 0; when IECIN1 input is used - 80 supply voltage analog quiescent current digital quiescent current analog supply current digital supply current VDDD = VDDA PD = 1; Tamb = 25 C PD = 1; Tamb = 25 C fs = 48 kHz; CLKSEL = 0; when IECIN1 input is used fs = 48 kHz; CLKSEL = 0 3.4 - - - - 5.0 - - 2.6 13 PARAMETER CONDITIONS MIN. TYP.
TDA1315H
MAX.
UNIT
5.5 10 10 - - -
V A A mA mA
mW
+70
C
IEC interface; pin IECIN1 (high sensitivity IEC input) AC input voltage (peak-to-peak value) 0.2 VDD V
0.5 - 2.4 - - - -
V
RESET, SCK, LCLK, LMODE AND SYSCLKI (HYSTERESIS INPUTS) negative-going threshold positive-going threshold input voltage hysteresis V V V
Clock and timing output reference voltage 2.1 V A A
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
BLOCK DIAGRAM
TDA1315H
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Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
PINNING SYMBOL RCfil Vref VDDA VSSA IECIN1 IECIN0 IECSEL IECO IECOEN TESTB TESTC UNLOCK FS32 FS44 FS48 CHMODE VDDD2 VSSD2 RESET PD CTRLMODE LADDR LMODE LCLK LDATA STROBE UDAVAIL TESTA COPY INVALID DEEM MUTE PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PADCELL E029 E029 E008 E004 E007 IPP04 IUP04 OPFH3 IUP04 IPP04 IPP04 OPP41A OPP41A OPP41A OPP41A OPP41A E008 E009 IDP09 IPP04 IUP04 IPP04 IPP09 IPP09 IOF24 IDP04 OPF23 IPP04 OPP41A IOD24 OPF23 IUP04 PLL loop filter input decoupling internal reference voltage output analog supply voltage analog ground high sensitivity IEC input TTL level IEC input DESCRIPTION
TDA1315H
select IEC input 0 or 1 (0 = IECIN0; 1 = IECIN1); this input has an internal pull-up resistor digital audio output for optical and transformer link digital audio output enable (0 = enabled; 1 = disabled/3-state); this input has an internal pull-up resistor enable factory test input (0 = normal application; 1 = scan mode) enable factory test input (0 = normal application; 1 = observation outputs) PLL out-of-lock (0 = not locked; 1 = locked); this output can drive an LED indicates sample frequency = 32 kHz (active LOW); this output can drive an LED indicates sample frequency = 44.1 kHz (active LOW); this output can drive an LED indicates sample frequency = 48 kHz (active LOW); this output can drive an LED use of channel status block (0 = professional use; 1 = consumer use); this output can drive an LED digital supply voltage 2 digital ground 2 initialization after power-on, requires only an external capacitor connected to VDDD; this is a Schmitt-trigger input with an internal pull-down resistor enable power-down input in the standby mode (0 = normal application; 1 = standby mode) select microcontroller/stand-alone mode (0 = microcontroller; 1 = stand-alone); this input has an internal pull-up resistor microcontroller interface address switch input (0 = 000001; 1 = 000010) microcontroller interface mode line input microcontroller interface clock line input microcontroller interface data line input/output strobe for control register (active HIGH); this input has an internal pull-down resistor synchronization for output user data (0 = data available; 1 = no data) enable factory (scan) test input (0 = normal application; 1 = test clock enable) copyright status bit (0 = copyright asserted; 1 = no copyright asserted); this output can drive an LED validity of audio sample input/output (0 = valid sample; 1 = invalid sample); this pin has an internal pull-down resistor pre-emphasis output bit (0 = no pre-emphasis; 1 = pre-emphasis) audio mute input (0 = permanent mute; 1 = mute on receive error); this pin has an internal pull-up resistor
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
SYMBOL I2SSEL SDAUX SD WS SCK I2SOEN SYSCLKI SYSCLKO VSSD1 VDDD1 CLKSEL RCint
PIN 33 34 35 36 37 38 39 40 41 42 43 44
PADCELL IUP04 IPP04 IOF24 IOF24 IOF29 IUP04 IPP09 OPFA3 E009 E008 IUP04 E029 auxiliary serial data input; I2S-bus
DESCRIPTION select auxiliary input or normal input in transmit mode serial audio data input/output; I2S-bus word select input/output; I2S-bus serial audio clock input/output; I2S-bus serial audio output enable (0 = enabled; 1 = disabled/3-state); this input has an internal pull-up resistor system clock input (transmit mode) system clock output (receive mode) digital ground 1 digital supply voltage 1 select system clock (0 = 384fs; 1 = 256fs); this input has an internal pull-up resistor integrating capacitor output
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
FUNCTIONAL DESCRIPTION Modes of operation With respect to the control of the device and the exchange of non-audio data, a microcontroller (host) mode and a stand-alone mode can be considered. The selection of the mode is performed at pin CTRLMODE. In the stand-alone mode, the device configuration is solely determined by pins. In the host mode an internal control register, or pins or both can be used to change the default settings. With respect to the direction of the digital audio data, the device can be operated in either a transmit or a receive mode under control of a microcontroller. In the stand-alone mode the device is only a receiver. In the receive mode the input signal can also be made available at the output pin IECO (feed-through) to ease the cascading of digital audio equipment. The device can be brought to standby mode at all times by activating the PD pin (power down). In this mode all functions are disabled, all outputs 3-stated, supply current is minimized and the contents of the register are saved. General For those applications where it is important to save power, the PD pin is provided, which, when activated, puts the TDA1315H in standby mode by disabling all functions and 3-stating all outputs, while saving register contents. As illustrated in Fig.1, the TDA1315H contains the following major functional blocks: * IEC input section * Biphase demodulator * Frame and error detection * Clock and timing section * IEC output section * Biphase modulator * Audio section (I2S-bus transceiver) * Non-audio section (control and FIFO) * User (microcontroller) interface. IEC INPUT SECTION There are two biphase signal inputs to the IEC input section. IECIN0 accepts TTL levels from, for example, an optical input device, while IECIN1 is designed for coaxial cable inputs and requires signal levels of minimum 200 mV (p-p) via an external coupling capacitor. The selection of the active input channel is performed by pin 1995 Jul 17 7 IEC OUTPUT SECTION
TDA1315H
IECSEL or by the control register or both. In the receive mode, the selected input signal is applied internally to the biphase audio output section to enable a feed-through function. BIPHASE DEMODULATOR In the biphase demodulator, the received signal (for details see Chapter "References"[1] and [2]) is converted to binary data and separated into audio and non-audio data for further processing in their dedicated sections. The demodulated input signal is also required for frame and error detection. FRAME AND ERROR DETECTION In the frame and error detection block, the framing information from the received biphase signal is retrieved to synchronize the biphase demodulator and to allow access to the audio and non-audio data bits. An out-of-lock condition of the PLL is flagged at UNLOCK. The validity of audio samples is indicated at pin INVALID. CLOCK AND TIMING SECTION In the clock and timing section, the timing information inherent to the received biphase signal is retrieved and a symmetrical master clock signal is generated and output at pin SYSCLKO. Depending on the mode of operation, the frequency of this master clock can be selected by pin CLKSEL, by the control register or both to be either 256fs or 384fs (fs = audio sampling frequency). This section contains all the circuitry of a Phase-Locked Loop (PLL), except for the loop filter components, which are connected externally to pins RCint and RCfil. When the input signal is interrupted, the oscillator will slowly drift to the centre frequency in order to keep the system operating on a proper frequency. In the transmit mode, all required timing signals are input at pin SYSCLKI and are derived from an externally supplied system clock of either 256fs or 384fs. The input HIGH time of that clock may be in the range between 30% to 70% of the clock period.
In the IEC output section, either the received (feed-through function) or the generated biphase signal is selected for output at pin IECO, depending on the receive/transmit mode. The output can be enabled/disabled by pin IECOEN, by the control register or both, and can drive a suitable optocoupler and a transformer in parallel.
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
BIPHASE DEMODULATOR In the biphase modulator section, audio and non-audio data are combined into subframes, frames and blocks, and encoded in the biphase-mark format during transmit mode. Although there are always 24 audio bits per sample in a subframe, the number of significant bits can be selected as 16, 18, 20 or 24 via the control register (host mode). AUDIO SECTION In the audio section, the left and right channel audio samples are taken from the demodulated data frames and are output serially in accordance with the I2S-bus format (for details see Chapter "References"[3] pins SD, SCK and WS) when the TDA1315H is in the receive mode (I2S-bus transmitter). The audio output signals are concealed or muted in case certain errors were detected during reception. Mute can be enforced by pin MUTE or via the control register (host mode) and affects, depending on the receive/transmit mode, the I2S-bus or IEC output signals. MUTE is internally synchronized with the audio data. In the transmit mode, there is an additional I2S-bus data input SDAUX made available to accept audio data from, for example, an ADC. This input can be selected either by pin I2SSEL, by the control register or both. The I2S-bus Port can be enabled/disabled by pin I2SOEN, by the control register or both. In the transmit mode, I2S-bus data and timing are supplied by an external source, the TDA1315H then becomes an I2S-bus receiver. In this event, selection of an I2S-bus source determines which signal is to be output at IECO. Although the phase relationship between system clock (SYSCLKI) and I2S timing (SCK) is not critical they must be synchronous with each other, i.e. be derived from the same source.
TDA1315H
Apart from detecting the out-of-lock condition of the PLL, received data is checked for the errors listed below. All detected errors will be flagged in the status register and two of them brought out to a pin. Depending on the type of error, different measures are taken. * Validity flag set. This error condition is also output at pin INVALID, simultaneously with the data. The corresponding audio sample is not modified. * Parity check error. A concealment operation is performed on both audio channels (left and right), i.e. the last correctly received stereo sample is output again. * Biphase violation (other than preambles). A concealment operation (hold) is performed on both audio channels (left and right), i.e. the last correctly received stereo sample is output again. * PLL is out-of-lock. This error condition is also output at pin UNLOCK. Both audio output channels (left and right) are set to zero (mute). The error condition is sampled with the HIGH-to-LOW transition of WS, i.e. muting becomes effective when the outputting of a stereo sample begins. When the PLL has locked again, muting is released only after a full block of audio samples has been received, free of errors.The INVALID output will always be set to LOW simultaneously with this muting. In the receive mode it is possible to select the auxiliary I2S-bus data input SDAUX for output at pin SD. However, there will be no suitable system clock available in the event of an open IEC input or a disabled IEC source and output SD will be muted when the TDA1315H is not in lock. Regardless of which source is selected, a MUTE command will always mute the output signal at pin SD and set the INVALID output to LOW regardless of the validity bit value. When mute command is disabled, muting will be released when the outputting of the next stereo sample begins.
Receive mode
The IEC subframe format defines 20 bits for an audio sample, plus 4 auxiliary bits, which can be used to extend the word length. By default, all 24 data bits per sample are output via the I2S-bus Port. This can be changed, however, to 16, 18 or 20 bits via bits 2 and 3 in byte 1 of the control register. The remaining bits will then be zero. The serial audio clock frequency at pin SCK is 64 x fs, i.e. there are 32 clock pulses per audio sample (left or right channel).
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Table 1 Summary of validity and muting in the receive mode INPUT CONDITIONS(1) PLL LOCKED X No X Yes Yes Yes Note 1. X = don't care. When the I2S-bus output Port is disabled by pin I2SOEN in the stand-alone mode, pins WS, SCK, SD and INVALID will immediately become 3-state. If, however, this is performed in the host mode via the I2SOEN pin or the corresponding bit in the control register, only SD and INVALID will become 3-state immediately. Pins WS and SCK will only become 3-state after the rising edge of STROBE when the STROBE pulse changes the setting from receive to transmit mode. Thus in the host mode, when remaining in the receive mode, I2SOEN only influences the SD and INVALID pins. Pins WS and SCK are always enabled. When the I2S-bus output Port is re-enabled, data output will start with the beginning of a new stereo sample. MUTE ACTIVATED X X yes no no no SDAUX SELECTED X X X no no yes I2SOUT ENABLED no yes yes yes yes yes VALIDITY BIT X X X 0 1 X
TDA1315H
OUTPUTS INVALID 3-state 0 0 0 1 0 SD 3-state 0 0 IEC IEC SDAUX
influences only the data pin SD. This allows for three different configurations: * Transmit mode #1, I2SOEN = 1, I2SSEL = 1. In this instance, I2S-bus timing and data are derived from an external source and entered at pins WS, SCK and SD. Output will be at pin IECO, if IECOEN permits. * Transmit mode #2, I2SOEN = 1, I2SSEL = 0. In this instance, I2S-bus timing is derived from an external source and entered at pins WS and SCK and is also supplied to another I2S-bus source, such as an ADC. Data from that other I2S-bus source is entered at pin SDAUX. Output will be at pin IECO, if IECOEN permits. In this instance, I2SSEL acts as a source selector for pins SD and SDAUX. * Transmit mode #3, I2SOEN = 0, I2SSEL = 0. In this instance, I2S-bus timing is derived from an external source and entered at pins WS and SCK and is also supplied to another I2S-bus source, such as an ADC. Data from the other I2S-bus source is entered at pin SDAUX. Output will be at pin IECO, if IECOEN permits, and at pin SD. In this mode, SDAUX data is available both at the IEC output (a type of digital monitor function) and on the I2S-bus (e.g. for digital signal processing purposes). The remaining combination (I2SOEN = 0, I2SSEL = 1) is not used. WS, SCK and SD are then 3-state. Because the SDAUX input normally receives a signal from an ADC, the signal at pin INVALID will not be interpreted when this input is selected. All samples are assumed to be valid. In all transmit modes, INVALID is an input pin.
Transmit mode
Although the IEC subframe format supports up to 24 bits per audio sample, the number of significant bits can be selected as 16, 18, 20 or 24 via the control register. Because the I2S-bus Port then operates as a receiver, the timing has to be selected so that all data bits can be received. Any bits unused or unsupplied will be set to logic 0. The information regarding audio samples that may be unreliable or invalid has to be entered at pin INVALID simultaneously with the data input to pin SD. The timing will be the same as in the CD decoder ICs (e.g. the EFAB signal of the SAA7310, see Chapter "References"[5]. As the I2S-bus Port is used as an input, it must be disabled by the correct combination of pin I2SOEN and the corresponding bit in the control register. The pins WS and SCK are set to 3-state on the rising edge of STROBE, whenever the transmit mode is activated. I2SOEN
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
Whenever MUTE is activated in any of the transmit modes, the audio data of the IEC output signal will be muted and the validity bit set to logic 0, regardless of the INVALID input value. When SDAUX is selected, MUTE will also affect the output at pin SD. Table 2 Summary of validity and muting in the transmit mode INPUT CONDITIONS(1) MUTE ACTIVATED No No No Yes Note 1. X = don't care. NON-AUDIO SECTION In the non-audio section, the first 30 channel status bits are taken from each block of data. A selection of 16 bits is then assembled as two bytes and transferred to the user interface. In the event of an incorrect IEC signal, i.e. no consumer mode, an error will be flagged at pin CHMODE. The error signal will return to its passive state after a full block of consumer mode data has been received. The user data bits are searched for the beginning of a `message' (see Section "User data"), which is then stored bytewise in a buffer that can be read by an external microcontroller via the user interface. In the transmit mode, channel status and user data bits are taken from an internal buffer that has been written to by an external microcontroller via the user interface. These bits are required for frame composition in the biphase modulator. The non-audio section supports only the consumer mode of the "IEC 958" specification and handles the channel status and user data information. The non-audio section can be operated in the stand-alone mode (receive only) and the host mode (transmit/receive). In the stand-alone mode, a few bits from the channel status are brought out to pins, the user data is not available. In the host mode, channel status and user data are exchanged using a microcontroller. After a RESET in the host mode, the TDA1315H provides general format by default. exchanged using an external microcontroller. The mapping of the channel status bits into these two bytes is given in Tables 3 and 4. All SCMS operations (Serial Copy Management System) will be performed in the microcontroller and no manipulation in the TDA1315H is possible. Bit 0 is always the first bit on the user interface. In the receive mode, an error signal is generated at pin CHMODE if a professional mode signal is received. Even then, two bytes of information, mapped as defined in Tables 3 and 4, are generated for output. Although there are two bytes of channel status available for output, only the first byte can be read. To identify future modes of the channel status, both mode bits (bits 6 and 7 in the channel status) are available (inverted) from the TDA1315H status register. The channel status is created from the left channel subframes of the IEC signal (preambles `B' and `M'). Whenever the channel status, as defined in Tables 3 and 4 (16 bits), differs from the previously received channel status, a bit will be set in the TDA1315H status register. This helps to reduce the data traffic by enabling the microcontroller to read the channel status only after it has changed. In the transmit mode, the microcontroller supplies consumer mode (Mode 0) channel status data as described in Table 3. Both bytes need to be transferred. SDAUX SELECTED no no yes X INVALID INPUT 0 1 X X IEC OUTPUT SIGNAL VALIDITY BIT 0 1 0 0 AUDIO BITS from SD from SD from SDAUX 0
Channel status
The channel status consists of 30 bits, a number of which are reserved for future standardization. The 16 most significant bits (MSBs), arranged as two bytes, are 1995 Jul 17 10
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Table 3 BIT First byte of transferred channel status DESCRIPTION BIT IN CHANNEL STATUS 29 and 28 25 and 24 3 2 1 0
TDA1315H
0 and 1 clock accuracy 2 and 3 sample frequency 4 5 6 7 Table 4 BIT 0 1 2 3 4 5 6 7 pre-emphasis copyright audio/data consumer/professional use
Normally, the exchange of user data between the TDA1315H and the microcontroller is based on the general format described above. In the event of CD subcode, this means that 96 bytes need to be transferred for each subcode frame. In order to reduce the amount of data traffic, it is possible to separate the Q-channel bits from the user data and transfer only them. This mode can be enabled by a bit in the control register and leads to the transfers of only 12 bytes per subcode frame. As there is no check in the TDA1315H whether user data is from a CD source, this Q-channel decoding can be employed whenever the user data format permits.
Second byte of transferred channel status DESCRIPTION category code category code category code category code category code category code category code category code BIT IN CHANNEL STATUS 15 14 13 12 11 10 9 8
Receive mode
User data bits are extracted from the received IEC subframes and searched for the beginning of a message. When Q-channel decoding is disabled (in the control register), the data bytes of a message are stored in a buffer for subsequent external interpretation or processing. Any 0 bits between information units and between messages are skipped. It is essential to maintain synchronization of messages, even if not all bytes of a message can be exchanged with the microcontroller in a single transfer, or if there are several messages in the buffer. When user data is transferred in the general format described earlier, the beginning of a message is indicated in the buffer by a 1 bit in the MSB position of the first byte of that message. In all subsequent bytes of the same message, the MSB will be zero. This is illustrated in Table 5 for the CD subcode. The user data buffer is implemented as a FIFO (First-In, First-Out) with a size of 128 bytes. This allows the storing of a full CD subcode frame. A synchronization signal at pin UDAVAIL supports the transfer of user data to the microcontroller. This signal goes LOW when there is at least 1 byte of user data in the buffer, and returns HIGH only after the last received byte has been read. This is illustrated in Fig.3. Based on the timing of the CD subcode, the microcontroller should start reading data within 17 ms after UDAVAIL has gone LOW, otherwise the buffer will fill completely and the most recent data will be lost.
User data
In principle, the user data bits may be used in any way required by the user. In order to guarantee compatibility between signals of any source, attempts have been made for the standardization of a user data format. The basic idea is to transfer `messages' that consist of `information units'. As messages are, typically, asynchronous with the IEC audio block structure, their transfer relies on software protocol. Currently, the applications for CD subcode and DAT have been accepted. Their general format complies with that protocol and can be described as follows: * User data is transferred in the form of messages. * Messages consist of information units, i.e. groups of 8 bits (bytes). * Messages are separated by more than 8 zero bits (0). * Information units within a message may be separated by 0 up to and including 8 zero bits. * The MSB of each byte is sent first in the user data channel. * The MSB of each byte is a 1-bit (1, start bit). * For CD subcode, one byte consists of bits 1QRSTUVW. 1995 Jul 17 11
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Table 5 MSB 0 1 0 0 0 0 0 0 1 0 0 0 .. Q1 Q2 Q3 .. .. Q95 Q96 Q1 Q2 Q3 .. .. R1 R2 R3 .. .. R95 R96 R1 R2 R3 .. Synchronization of user data USER DATA .. S1 S2 S3 .. .. S95 S96 S1 S2 S3 .. .. T1 T2 T3 .. .. T95 T96 T1 T2 T3 .. .. U1 U2 U3 .. .. U95 U96 U1 U2 U3 .. .. V1 V2 V3 .. .. V95 V96 V1 V2 V3 .. LSB .. W1 W2 W3 .. .. W95 W96 W1 W2 W3 ..
TDA1315H
FUNCTION - start of message - - - - - - start of next message - - -
Although the MSB is first within the IEC user data channel, the LSB is sent first on the user interface to be compatible with other data, i.e. the first byte of a subcode user data frame will be output as follows: 1. Bit sent = W1. 2. Bit sent = V1. 3. Bit sent = U1. 4. Bit sent = T1. Table 6 Layout of Q-channel data
5. Bit sent = S1. 6. Bit sent = R1. 7. Bit sent = Q1. 8. Bit sent = 1. When Q-channel decoding is enabled, only the Q-channel bits are taken from the user data frame and stored in the buffer. Again, any separating 0 bits are skipped. Table 6 shows how data is arranged in the buffer.
MSB .. Q89 Q1 Q9 Q17 .. .. Q89 Q1 .. .. Q90 Q2 Q10 Q18 .. .. Q90 Q2 .. .. Q91 Q3 Q11 Q19 .. .. Q91 Q3 .. ..
USER DATA .. Q93 Q5 Q13 Q21 .. .. Q93 Q5 .. .. Q94 Q6 Q14 Q22 .. .. Q94 Q6 .. .. Q95 Q7 Q15 Q23 .. .. Q95 Q7 .. Q92 Q4 Q12 Q20 .. .. Q92 Q4 ..
LSB .. Q96 Q8 Q16 Q24 .. .. Q96 Q8 ..
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
In this instance, synchronization of Q-channel frames must be maintained by the microcontroller. It is recommended to read decoded Q-channel data in groups of 12 bytes otherwise synchronization of subcode frames may be lost quickly. Again, the data transfer is supported by the signal at pin UDAVAIL. This time it goes LOW when there is at least one full frame (12 bytes) of Q-channel data in the buffer, and goes HIGH again, when less than 12 bytes are in the buffer. This is illustrated in Fig.4. An initial synchronization can be obtained by clearing the buffer via the control register, then start counting bytes modulo 12. Again, the LSB is sent first on the user interface, i.e. the first byte of a Q-channel frame will be output as follows: 1. Bit sent = Q8. 2. Bit sent = Q7. 3. Bit sent = Q6. 4. Bit sent = Q5. 5. Bit sent = Q4. 6. Bit sent = Q3. 7. Bit sent = Q2. 8. Bit sent = Q1. Writing to the buffer is disabled when the FIFO is full. It is re-enabled when there is at least 1 byte free. Any data overrun condition will be flagged as an error in the status register. When this has occurred, the appropriate strategy for data handling is decided by the microcontroller. It can, for example, clear the buffer via the control register, thereby discarding all remaining data, or it can start reading data rapidly. Clearing the buffer turns UDAVAIL HIGH. The response to reading data is the same as described previously, depending on the mode of reception, i.e. Q-channel decoding or normal message protocol. For the period that the user data register is selected, the microcontroller has to poll UDAVAIL each time after reading one byte in normal mode, or 12 bytes in Q-channel mode. Possible actions by the microcontroller are as follows: * If UDAVAIL = 0: reading the next byte in normal mode or the next 12 bytes in Q-channel mode. * If UDAVAIL = 1: either wait until UDAVAIL goes LOW and continue reading user data byte(s), or write data, read other data or deselect the TDA1315H by foreign addressing. - Remark: it is allowed to address the TDA1315H for reading user data again when UDAVAIL is still HIGH, but it is forbidden to apply clock pulses until UDAVAIL has gone LOW. 1995 Jul 17 13
TDA1315H
Remark: whenever the buffer is empty (UDAVAIL = 1), normally zeroes will be read, even when the microcontroller tries to read more bytes. Doing so, however, poses the risk of reading not all zeroes. In this event new data is stored in the buffer during reading, thereby losing synchronization. To assure correct information will be read, the microcontroller should perform an addressing sequence (not necessarily to the TDA1315H), whenever an UDAVAIL HIGH is detected before reading further.
Transmit mode
User data bits are supplied by the microcontroller in the general message format only, Q-channel encoding is not available in the TDA1315H. Again, UDAVAIL can be used to synchronize transfers. It goes HIGH, when the buffer contains at least 112 bytes, and goes LOW only when there are no more than 16 bytes in the buffer. This is illustrated in Fig.5. Thus, after UDAVAIL has gone LOW, the microcontroller can write a full CD subcode frame (96 data bytes plus 2 synchronization bytes) to the buffer without needing to poll the state of pin UDAVAIL. In the event that no data are available in the buffer, the user data bits in the IEC output signal will be set to zero. Should the microcontroller attempt to write more data than the buffer can hold, writing will be disabled and the data overrun bit set in the status register. Any bytes that have been transferred but not written into the buffer are lost. Four zero bits will be inserted automatically between user data bytes (information units). The gap between messages can be achieved by writing a single byte containing all zeroes to the buffer. USER INTERFACE The user interface is an interface between the data processing sections of the TDA1315H and the user. The basic mode of operation (control by a host or stand-alone operation) is selected by pin CTRLMODE. In the host mode, all data, control and status information is, in principle, exchanged with a microcontroller although the device configuration can also be changed by pin control. Up to 2 TDA1315Hs can be used on the same user interface by setting different device addresses via the LADDR pin. In the stand-alone mode (receive only), no microcontroller is needed because important information is brought out to pins FS32, FS44 and FS48, being an indication of sample frequency, copyright protection (COPY) (see Chapter "References"[2]) and use of pre-emphasis (DEEM).
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Stand-alone mode
In this mode, the TDA1315H is automatically configured as a receiver. The configuration, i.e., the mode of operation of the device, is determined by pins CTRLMODE, IECSEL, IECOEN, CLKSEL, I2SSEL and I2SOEN. Because all of the pins have internal pull-up resistors, the default configuration can be changed by pulling a pin LOW. The output signals listed below are provided from the channel status. However, all of them are switched off when the PLL is not locked. This includes the situation where no IEC input signal is available: * Sample frequency is 32 kHz (pin FS32) * Sample frequency is 44.1 kHz (pin FS44) * Sample frequency is 48 kHz (pin FS48) * Copyright status bit (pin COPY) * Pre-emphasis bit (pin DEEM). As there will be no output signals from the channel status in the event that non-consumer IEC signals are received, the I2S-bus output will still output data in 24 bits format. An LED can be connected to pin CHMODE to provide an indication of such a situation.
TDA1315H
* LDATA to microcontroller interface data line. * LCLK to microcontroller interface clock line. * LMODE to microcontroller interface mode line. * LADDR to microcontroller interface address switch. Two different modes of operation can be distinguished: 1. Addressing mode. 2. Data transfer mode. The addressing mode is used to select a device for subsequent data transfer and to define the direction of that transfer as well as the source or destination registers. The addressing mode is characterized by LMODE being LOW and a burst of 8 clock pulses at LCLK, accompanied by 8 data bits. The fundamental timing is illustrated in Fig.6. Data bits 0 to 1 indicate the type of subsequent data transfer as given in Table 7. The direction of the channel status and user data transfers depends on the transmit/receive mode. Data bits 2 to 7 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the TDA1315H is 000001 (LADDR = 0) or 000010 (LADDR = 1). Should the TDA1315H receive a different address, it will immediately 3-state the LDATA pin and deselect its microcontroller interface logic. A dummy address of 000000 is defined for the deselection of all devices that are connected to the serial microcontroller bus.
Host mode
In this mode, the exchange of data and control information between the TDA1315H and a microcontroller is via a serial hardware interface, which comprises the following pins:
Fig.3 User data handshake.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
Fig.4 Q-channel handshake.
Fig.5 Transmit mode handshake.
Fig.6 Addressing mode timing.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Table 7 Selection of data exchange BIT 1 0 0 1 1 BIT 0 0 1 0 1 TRANSFER channel status user data control status
TDA1315H
DIRECTION input/output input/output input output
In the data transfer mode, the microcontroller exchanges data with the TDA1315H after it has addressed the device and defined the type of data for that exchange. The selection remains active until the TDA1315H receives a new type of data or is deselected. The fundamental timing of data transfers is illustrated in Fig.7, where LDATA denotes the data from the TDA1315H to the microcontroller (LDATA read). The timing for the opposite direction is essentially the same as in the addressing mode (LDATA write).
Fig.7 Data transfer mode timing. All transfers are bytewise, i.e. they are based on groups of 8 bits. Data will be stored in the TDA1315H after the eighth bit of each byte has been received. It is possible to read only the first byte of the channel status and of the TDA1315H status register. A multi-byte transfer is illustrated in Fig.8. As some other devices, which are expected to connect to the same microcontroller bus lines, require an indication of when 8 bits have been transferred, a so-called halt mode has been defined. It is characterized by the following conditions: LMODE = LOW, LDATA = 3-state and LCLK = HIGH. The TDA1315H does not need this mode to distinguish one byte from the next, however, it will not make any difference when this occurs. When not used, there is no need to increase the time between the last LCLK pulse of a byte and the first LCLK pulse of the next byte.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
Fig.8 Multi-byte transfer.
DAIO control
Under microcontroller control, there is also a transmit mode available. Therefore, setting the device configuration is slightly different from the stand-alone mode. Most functions or modes can be set by pins or by the control register or by both. Negative logic is used to implement this `OR' function. The initial setting of the control register is all ones. For most functions, the TDA1315H can be configured only by pins, as explained for the stand-alone mode. The principle of this type of control is illustrated in Fig.9. However, for changing CLKSEL, I2SSEL and the receive/transmit mode, there is a configuration register, which is updated only by an externally supplied STROBE signal. This allows synchronization with other ICs. At pin LDATA, control information is first entered serially into a shift register and then latched in the control register when complete. The bits of the second byte (6 are used) of this register are internally ORed with their corresponding pins, so that either a LOW or a logic 0 bit will result in a logic 0 state (active LOW). These combined states are then entered in the status register. The resulting CLKSEL and I2SSEL information is supplied to the configuration register, i.e. these bits will only be executed in the TDA1315H, together with the receive/transmit bit, after a STROBE has been received. This applies to the host mode. In the stand-alone mode, the configuration register is transparent and any configuration changes are executed immediately. When the TDA1315H status is read, the contents of the status register are output serially at pin LDATA, thereby reflecting the `OR' combination of configuration control bits and associated pins (negative
logic). The microcontroller is thereby able to determine whether a pin is open-circuit or tied to ground. When a STROBE is applied in the receive mode (to switch to transmit mode), the outputs WS and SCK are disabled one or two system clock periods after the rising edge of STROBE. At the same time SYSCLKO will be forced LOW and will be disabled one system clock later. In the transmit mode it is possible to set the receive/transmit bit to zero and then poll the locking status of the TDA1315H and wait with a STROBE until the TDA1315H is in-lock. This method can be used to check whether there is an IEC source, since the TDA1315H will not lock without one. It should be noted that the locking status bit and the UNLOCK pin are only valid, i.e. its value has a meaning, when you are in either the receive mode or the receive/transmit bit is set to zero in the transmit mode. When the configuration is changed to the receive mode, WS, SCK, INVALID and SYSCLKO outputs are enabled one or two system clock periods after the falling edge of STROBE. SYSCLKO will always be initially LOW, for a short time, and then pulses will appear always starting with the rising edge. In general WS and SCK outputs are always enabled/disabled simultaneously. Output INVALID will only be enabled when SD, WS and SCK are all enabled. The mode timing is illustrated in Fig.10. The control register consists of two bytes. The meaning of the control register bits is given in Tables 8 and 9. All bits default to a logic HIGH state after a reset to the TDA1315H. This requires a reset for proper initialization when CTRLMODE is changed after power-up. The LSB (bit 0) is always transferred first. 17
1995 Jul 17
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
Fig.9 Mode control.
Table 8 BIT 0 1 3 and 2
First byte of control register DESCRIPTION transmit/receive mode decode subcode Q-channel number of bits to transfer FUNCTION 0 = receive 1 = transmit 0 = enable 1 = disable 00 = 16 bits 01 = 18 bits 10 = 20 bits 11 = 24 bits 0 = clear 1 = leave as is 0 = undefined 1 = default 0 = undefined 1 = default 0 = undefined 1 = default
Table 9 BIT 0 1 2 3 4 5 6 7
Second byte of control register DESCRIPTION audio mute IEC output enable select IEC input I2S-bus output enable select I2S-bus source select clock frequency reserved reserved FUNCTION 0 = enabled 1 = disabled 0 = enabled 1 = disabled 0 = TTL level 1 = high sensitivity 0 = enabled 1 = disabled 0 = SDAUX 1 = SD 0 = 384fs 1 = 256fs 0 = undefined 1 = default 0 = undefined 1 = default
4(1) 5 6 7 Note
clear user data buffer reserved reserved reserved
1. Bit 4 is reset to HIGH after the TDA1315H has cleared the buffer and has either caused UDAVAIL to go HIGH in the receive mode or LOW in the transmit mode.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
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Fig.10 Mode switching and timing STROBE input.
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Status
The status register consists of two bytes. A description of the status register bits is given in Tables 10 and 11. After a reset all bits in the status register will be one. The various error conditions of the TDA1315H are reflected in bits 0 to 6 of the first byte. The error bits are set (LOW) when the corresponding error conditions occur, they are reset (HIGH) only after the register has been read by the microcontroller. Bit 7 reflects the active transmit/receive state. It is updated after the TDA1315H configuration, as determined by bit 0 of the first control register byte, has been changed. This allows verification of the mode change to, for example, release a mute signal after a successful change. Table 10 First byte of status register BIT 0 1 2 3 4 5 6 7 DESCRIPTION channel status mode PLL lock condition validity flag parity check biphase violation user data overrun channel status check direction of data FUNCTION 0 = professional 1 = consumer 0 = not locked 1 = locked 0 = error 1 = no error 0 = error 1 = no error 0 = error 1 = no error 0 = error 1 = no error 0 = change 1 = no change 0 = receive 1 = transmit 7(1) Note inverse mode bit (bit 6)
TDA1315H
Table 11 Second byte of status register BIT 0 1 2 3 4 5 6(1) DESCRIPTION audio mute IEC output enable select IEC input I2S-bus output enable select I2S-bus source select clock frequency channel status (bit 7) FUNCTION 0 = enabled 1 = disabled 0 = enabled 1 = disabled 0 = TTL level 1 = high sensitivity 0 = enabled 1 = disabled 0 = SDAUX 1 = IEC or CD 0 = 384fs 1 = 256fs 0 = bit 7 set 1 = bit 7 reset 0 = bit 6 set 1 = bit 6 reset
1. Bits 6 and 7 in the second byte of the status register contain the inversion of bits 7 and 6, respectively, of the channel status, which are used as mode bits.
Reset and standby mode
Figure 11 illustrates the timing for the toggling between normal and standby mode. In Figs 11 and 12, when activating PD or RESET, 0 ns can be taken for tON:OSC when the oscillator is running (e.g. receive mode). The TDA1315H uses its internal oscillator for the reset and standby function. This means that it is not necessary, in any mode, to apply a clock at the SYSCLKI input for the TDA1315H to perform the reset or standby function. For resetting the TDA1315H only a small pulse is necessary at the RESET input. The device then automatically starts the oscillator (in the event that it is not running). The system will then do a synchronous reset (internally) during approximately 3 internal clock periods. This tRESET starts after the falling edge of RESET or when the oscillator has started, whichever occurs last. Only when this resetting has been accomplished will the external pin programming (e.g. CLKSEL, I2SOEN etc.) be read by the TDA1315H. The TDA1315H is then ready for use.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
Fig.11 Standby mode timing.
Fig.12 RESET timing.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD IDD Vall II/O PARAMETER supply voltage (pins 3, 17 and 42) supply current per pin (pins 3, 17 and 42) voltage supplied to all pins input/output current on any pin except supply pins and pins 8, 12 to 16, 29 and 40 input current pins 12 to 16 and 29 input/output current pins 12 to 16 and 29 input/output current pin 8 input/output current pin 40 total power dissipation storage temperature operating ambient temperature electrostatic handling note 2 note 3 Notes without current limitations note 1 CONDITIONS - -0.5 - MIN. -0.5
TDA1315H
MAX. +6.5 50 V
UNIT mA
VDD + 0.5 V 10 mA
II II/O I8 I40 Ptot Tstg Tamb Ves
VO > VDD + 0.5 V; output disabled; note 1 VO < VDD + 0.5 V; note 1 note 1 note 1
- - - - - -65 -20 -2000 -200
10 20 60 80 500 +150 +70 +2000 +200
mA mA mA mA mW C C V V
1. In all events and, also, when applied voltages are below -0.5 V or above VDD + 0.5 V this current limitation should be taken into account to prevent device damage. 2. Human body model: pins 25, 27, 30, 31 and 35 to 37 = 1500 V; R = 1.5 k; C = 100 pF; 3 zaps positive and 3 zaps negative. 3. Machine model: R = 25 ; C = 200 pF; L = 0.5 A; 3 zaps positive and 3 zaps negative. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 80 UNIT K/W
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
CHARACTERISTICS VDDD1 = VDDD2 = VDDA = 3.4 to 5.5 V; Tamb -20 to +70 C; rise, fall, set-up and hold times are specified between 10% and 90% of full amplitude; delays between 50%; times to and from 3-state with RL = 1.5 k to 12VDD; typical values are valid at the typical supply voltage of 5 V unless otherwise specified. SYMBOL Supply VDD IDDD IDDA supply voltage digital supply current analog supply current VDDD = VDDA PD = 1; Tamb = 25 C PD = 1; Tamb = 25 C 3.4 - - 5.0 - - 5.5 10 10 V A A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
THE FOLLOWING PARAMETERS ARE TYPICAL FOR RECEIVE MODE; ALL OUTPUTS ENABLED (NOT LOADED); Tamb = 25 C; VDD = 5 V IDDD IDDA Ptot digital supply current analog supply current total power dissipation fs = 48 kHz; CLKSEL = 0 fs = 48 kHz; CLKSEL = 0; when IECIN1 input is used fs = 48 kHz; CLKSEL = 0; when IECIN1 input is used - - - 13 2.6 80 - - - mA mA mW
TTL input switching levels (without Schmitt-trigger) APPLICABLE TO PERIPHERAL TYPES: IPP04, IUP04, IDP04, IOF24 AND IOD24 VIL LOW level input voltage VDD = 3.4 V VDD = 4.5 V VDD = 5.5 V VIH HIGH level input voltage VDD = 3.4 V VDD = 4.5 V VDD = 5.5 V TTL input thresholds (with Schmitt-trigger) APPLICABLE TO PERIPHERAL TYPES: IPP09, IDP09 AND IOF29 VtHL negative-going threshold VDD = 3.4 V VDD = 4.5 V VDD = 5.5 V VtLH positive-going threshold VDD = 3.4 V VDD = 4.5 V VDD = 5.5 V Vhys hysteresis voltage VDD = 3.4 V VDD = 4.5 V VDD = 5.5 V Input pull-up and pull-down resistor values; note 1 APPLICABLE TO PERIPHERAL TYPES: IUP04, IDP04, IDP09 AND IOD24 Rpull pull-up or pull-down resistors VDD = 3.4 V VDD = 4.5 V VDD = 5.5 V 32 21 17 - - - 203 134 104 k k k 0.3 0.6 0.6 - - - - - - - - - - - - 0.6 0.6 0.8 - - - 1.9 2.4 2.4 - - - V V V V V V V V V - - - 1.5 2.0 2.0 - - - - - - 0.5 0.8 0.8 - - - V V V V V V
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Outputs sink and source capabilities APPLICABLE TO PERIPHERAL TYPES: OPF23, IOF24, IOD24, AND IOF29 (2 mA OUTPUTS) VOL LOW level output voltage VDD = 3.4 V; IO = 1.5 mA VDD = 4.5 V; IO = 2 mA VDD = 5.5 V; IO = 2.25 mA VOH HIGH level output voltage VDD = 3.4 V; IO = -1.5 mA VDD = 4.5 V; IO = -2 mA VDD = 5.5 V; IO = -2.25 mA APPLICABLE TO PERIPHERAL TYPE: OPP41A (4 mA OUTPUT) VOL LOW level output voltage VDD = 3.4 V; IO = 3 mA VDD = 4.5 V; IO = 4 mA VDD = 5.5 V; IO = 4.5 mA APPLICABLE TO PERIPHERAL TYPE: OPFH3 (12 mA OUTPUT) VOL LOW level output voltage VDD = 3.4 V; IO = 9 mA VDD = 4.5 V; IO = 12 mA VDD = 5.5 V; IO = 13.5 mA VOH HIGH level output voltage VDD = 3.4 V; IO = -9 mA VDD = 4.5 V; IO = -12 mA VDD = 5.5 V; IO = -13.5 mA APPLICABLE TO PERIPHERAL TYPE: OPFA3 (16 mA OUTPUT) VOL LOW level output voltage VDD = 3.4 V; IO = 12 mA VDD = 4.5 V; IO = 16 mA VDD = 5.5 V; IO = 18 mA VOH HIGH level output voltage VDD = 3.4 V; IO = -12 mA VDD = 4.5 V; IO = -16 mA VDD = 5.5 V; IO = -18 mA Input and 3-state (OFF state) leakage currents APPLICABLE TO PERIPHERAL TYPES: IPP04 AND IPP09 |ILI| |IOZ| input leakage current VI = 0 or 5.5 V; VDD = 5.5 V - VO = 0 or 5.5 V; VDD = 5.5 V - - - 1 5 A A - - - 2.9 4.0 5.0 - - - - - - 0.5 0.5 0.5 - - - V V V V V V - - - 2.9 4.0 5.0 - - - - - - 0.5 0.5 0.5 - - - V V V V V V - - - - - - 0.5 0.5 0.5 V V V - - - 2.9 4.0 5.0 - - - - - - 0.5 0.5 0.5 - - - V V V V V V
APPLICABLE TO PERIPHERAL TYPES: OPF23, OPFH3, OPFA3, OPP41A, IOF24 AND IOF29 3-state leakage current
IEC interface; note 2; (for timing see Chapter "References", item 1) IECO (PIN 8) tdIEC output delay with respect to IECINx receive mode 2Tc - 3Tc + 50 ns
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
SYMBOL IECIN1 (PIN 5) Vi(p-p) Ii Vbias
PARAMETER
CONDITIONS
MIN. -
TYP.
MAX.
UNIT
AC input voltage (peak-to-peak value) input current DC bias voltage VI = 0 or 5 V; VDD = 5 V
0.2 - -
VDD - -
V A V
550 0.5VDD
I2S-bus interface; (for timing see Chapter "References", item 3) SD INPUT/OUTPUT (PIN 35) tdSDAUX output delay with respect to SDAUX - - 50 ns
Microcontroller interface (see Figs 6 and 7) T tHC tLC tSU;AD tHD;AD tSU;MA tHD;MA tSU;MT tHD;MT tSU;DA tHD;DA tEN;DT tHD;DT t3DT thalt tH;SB tL;SB tSU;SB tHD;SB tDBIT tEN;SD t3SD tEN;WS t3WS tEN;CO 1995 Jul 17 LCLK period LCLK HIGH period LCLK LOW period LADDR set-up time LADDR hold time LMODE set-up time LMODE hold time LMODE set-up time LMODE hold time LDATA set-up time LDATA hold time LDATA enable time LDATA hold time LDATA disable time LMODE halt time addressing mode addressing mode halt mode halt mode write and addressing mode write and addressing mode data read mode data read mode; note 3 data read mode Tc + 50 25 25 25 25
1 (T 2c 1 (T 2c
- - - - -
- - - - - - - - - - - 50 Tc + 50 50 - - - - - 3Tc + 50 2Tc + 50 Tc + 50 2Tc + 50 2Tc + 50 2Tc + 50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
+ 50) - + 50) - - - - - - - - - - - - - - - - - - -
25 25 25 25 -
1 T 2c
- 0
Mode switching and STROBE (see Fig.10) STROBE HIGH time STROBE LOW time set-up time before STROBE delay LCLK to internal bit SD enable time SD and INVALID disable time WS, SCK and INVALID enable time WS and SCK disable time SYSCLKO enable time 25 for pins or bits 3Tc + 50 3Tc + 50 -Tc + 50 2Tc + 50 2Tc Tc - Tc Tc Tc ns ns ns ns ns ns ns ns ns ns
hold time after STROBE for pins or bits control register
Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
SYMBOL t3CO tLE;CO tLD;CO tHD;CI tON;OSC tOFF;OSC t3OP tEN;OP t3CR tEN;CR tHR tRESET SYSCLKI SYSCLKO t/t koL koH 2frL 2frH fcL fcH
PARAMETER SYSCLKO disable time SYSCLKO LOW time SYSCLKO LOW time SYSCLKI hold time oscillator start-up time oscillator switch-off time
CONDITIONS when enabled when disabled Cref in F; note 4
MIN. 2Tc 1 T 2s Tc - Ts 3Tc + 50 0 2Tc - - - - - - - - - - - - - -
TYP.
MAX. 3Tc + 50 Tc + 50 -
1 10Cref
UNIT ns ns ns s ns
1.5Ts + 50 ns
3Tc + 50 Tc + 50 Tc + 50 2Tc + 50 Tc + 50 - 2
Standby mode (see Fig.11) outputs disable time outputs enable time SYSCLKO disable time SYSCLKO enable time receive mode receive mode ns ns ns ns
Tc -
RESET (see Fig.12) RESET HIGH time internal RESET time 25 - ns s
Clock and timing (pins SYSCLKI and SYSCLKO) input clock duty factor output clock duty factor SYSCLKO output clock jitter VCO conversion gain VCO conversion gain VCO frequency tuning range VCO frequency tuning range VCO centre frequency VCO centre frequency VDDA < 10 V RCfil to SYSCLKO; CLKSEL = 1 RCfil to SYSCLKO; CLKSEL = 0 at SYSCLKO; CLKSEL = 1 at SYSCLKO; CLKSEL = 0 at SYSCLKO; RCfil = Vref; CLKSEL = 1 at SYSCLKO; RCfil = Vref; CLKSEL = 0 30 45 - - - - - - - 50 50 50 x 10-6 70 55 - - - - - - - rad/s/V rad/s/V MHz MHz MHz MHz % %
225 x 106 250 x 106 16 22 12.5 19
Vref OUTPUT (PIN 2) Vref Iref VtrL VtrH |ILI| output reference voltage output reference current Vref = 0 V fs = 32 to 48 kHz; CLKSEL = 1 fs = 32 to 48 kHz; CLKSEL = 0 VI = 0 or 5.5 V; VDD = 5.5 V; TESTB = 1 - - - - - 2.1 28 - - - - 1 V A mV mV A
RCfil INPUT (PIN 1) input tuning voltage input tuning voltage input leakage current 100 150 -
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TDA1315H
SYMBOL Rtr
PARAMETER transmission-gate resistor
CONDITIONS Vref = 2.1 V; VDD = 5 V; note 5 -
MIN. 1
TYP. -
MAX.
UNIT M
RCint OUTPUT (PIN 44) Co Ich(fr) Ich(ph) ficlk parallel output capacitance output charge current output charge current frequency detector loop phase detector loop - - - - - 2(8) 4(8) 12.42(7) 18.63(7) 5 12 24 - - - - - - - - - 16(6) 24(6) 8.06(7) 12.09(7) 26(8) 37(8) pF A A MHz MHz
SYSCLKI INPUT (PIN 39); TRANSMIT MODE; VDD = 3.4 TO 5.5 V input clock frequency CLKSEL = 1; note 6 CLKSEL = 0; note 6 SYSCLKO OUTPUT (PIN 40); RECEIVE MODE; VDD = 3.4 TO 5.5 V foclk(l) foclk(u) Notes 1. Pull-up specified at input to VSS, pull-down specified at input to VDD. 2. Most timing specifications are related to clock periods. Two basic periods are of importance: a) Tc, this is the internal clock period of the TDA1315H being 1128fs seconds. b) Ts, this is the system clock period such as SYSCLKI or SYSCLKO, being 1256fs or 1384fs seconds. c) It should be noted that in the receive mode clock frequencies are only reliable when the TDA1315H is in-lock. 3. In the transmit mode, when SYSCLKI is 384fs and 30% or 70% duty cycle: tHD;DT is 0.43Tc minimum. 4. This time strongly depends on the external decoupling capacitor connected to Vref (pin 2). When the capacitor is initially empty, it must first be charged before the oscillator can start. 5. Internally this resistor will be connected between RCfil and Vref, when there is no signal on the selected IEC input in receive mode, or when the oscillator is turned off. This is to prevent the oscillator to drift to extreme low or high frequencies. See also Chapter "Characteristics"with regards to foclk(l) and foclk(u). 6. These figures are theoretical limits for the TDA1315H. In the application, the maximum frequencies at fs = 48 kHz will be fixed. Consequently ficlk = 12.288 MHz (CLKSEL = 1) and ficlk = 18.432 MHz (CLKSEL = 0). 7. These frequencies mean that the TDA1315H is guaranteed to lock in the range fs = 31.5 to 48.5 kHz over the whole supply voltage range and specified temperature range. 8. These are the limit frequencies that the internal oscillator may reach under extreme conditions when the VCO input (pin RCfil) would be controlled far beyond its normal tuning range. An internal resistor however, prevents that these frequencies can be reached when there is no signal to lock-on to. See also Chapter "Characteristics" regarding Rtr. QUALITY SPECIFICATION In accordance with "SNW-FQ-611E". The number of this quality specification can be found in the "Quality Reference Pocketbook". The pocketbook can be ordered using the code 9398 510 34011. output clock frequency lower limit oscillator output clock frequency upper limit oscillator CLKSEL = 1 CLKSEL = 0 CLKSEL = 1 CLKSEL = 0 MHz MHz MHz MHz
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
TEST AND APPLICATION INFORMATION
TDA1315H
Figures 13 to 15 indicate typical systems environment of the TDA1315H. They are intended to give examples of which external blocks may be added to compose a system for particular requirements. The loop filter configuration and values in the examples meet the requirements for mid-end and high-end audio applications. Test information Table 12 Test pin functions TEST PIN TESTA = 0 TESTA = 1 TESTB = 0 TESTB = 1 TESTC = 0 TESTC = 1 normal application operation test mode i.e. system clock equals SYSCLKI normal mode when TESTA = 1 scan mode when TESTA = 1; high-ohmic resistor between RCfil and Vref pins always disabled normal operation CHMODE equals system clock; IECO equals IECIN1 slicer output; RAM test enabled DESCRIPTION
Table 13 Implemented test scan chains SCAN NUMBER 1 2 3 4 5 6 7 8 LENGTH (BITS) 54 54 54 54 53 53 51 31 SCAN INPUT IECSEL IECOEN LADDR MUTE LMODE STROBE I2SSEL CLKSEL FS32 FS44 FS48 COPY CHMODE UDAVAIL DEEM UNLOCK OUTPUT ACTIVE EDGE OF SYSCLKI negative negative negative negative negative negative negative positive
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Stand alone application (receive only) A very simple implementation of the stand-alone application is illustrated in Fig.13. In simple terms, it is an IEC-to-analog converter. The IEC signal is input via a shielded cable and enters the TDA1315H via its high-sensitivity input. The audio output is supplied to a DAC via the enabled I2S-bus Port, the DEEM output can
TDA1315H
be used to switch a de-emphasis network in and out of the signal path. The system clock frequency can be selected and is available should any digital filters in the DAC block require such a clock. The sample frequency of the received signal together with any out-of-lock condition of the phase-locked loop and the presence of a professional mode IEC signal can be displayed with LEDs.
When in a system both IECIN1 and IECIN0 inputs are used, the signal that is applied to the IECIN0 input must be kept away from the IECIN1 input on the printed-circuit board. Steep slopes of the IECIN0 input can be seen by the sensitive adjacent IECIN1 input. An extra capacitance parallel to the 75 resistor, close to the TDA1315H, can help reduce the crosstalk if required. A suitable value is 180 pF.
Fig.13 Simple stand-alone application.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Microcontroller based application (receive and/or transmit) The microcontroller-based application is illustrated in Fig.14. Functional blocks are shown for both the receive and the transmit mode. Here, the IEC signal is input via an optical fiber link and an associated optocoupler and enters the TDA1315H at its TTL-level input. The I2S-bus output signal is applied to a digital signal processing module, which may contain signal processors, DACs, a recording device etc. An ADC can be an optional source for that module. As the microcontroller can obtain all status information and data via the serial bus, it will provide
TDA1315H
display information and also will control the whole system, including the receive/transmit switch. For simplicity reasons, pin-based mode selection is not shown in this diagram. In the transmit mode, both system clock and I2S-bus timing are derived from a central timing block. The IEC output signal feeds an optical fiber link via a suitable optocoupler. Concerning the wide supply voltage range of the TDA1315H, it is not possible to have a transformer-coupled IEC output that fulfils the "IEC 958" standard over the full supply voltage range. The output will have an amplitude of 0.5 V (p-p) with a tolerance of 20%.
Fig.14 Microcontroller-based application.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
Transmit mode only application (also possible without microcontroller) In Fig.15 an example is given, how the TDA1315H can be operated as a transmitter without microcontroller. When the CTRLMODE pin is LOW, a reset applied to theTDA1315H will result in a default transmit mode. When the user is not interested in sending non-default channel status data (zeros) or user data, it remains always possible to encode audio data at the I2S bus to the IEC output. When no microcontroller is used, the TDA1315H will remain fully pin programmable when STROBE is connected to supply permanently.
TDA1315H
When the receive mode is not used, a dedicated loop-filter for the PLL is not necessary. However, for correct operation the TDA1315H does need a functional oscillator. The minimum configuration is defined by keeping pin 44 (RCint output) floating and connecting pin 1 (RCfil input) to pin 2 (Vref output). For the resetting and standby functions the oscillator will operate correctly.
Fig.15 Transmit-mode-only application.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
REFERENCES 1. "Digital audio interface", first edition 1989-03, international standard "IEC 958". 2. "Digital audio interface for domestic use", Philips/Sony, September 1983. 3. "I2S-bus specification", release 2-86, Philips export B.V., order number 9398 332 10011. 4. "Amendment to document IEC 958: Digital audio interface", Project number. 84.11.02107.
TDA1315H
5. "SAA7310, development data sheet", Philips Semiconductors, October 1987, order number 9397 153 90142.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
TDA1315H
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
SOLDERING QFP Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these cases reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Manual" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
TDA1315H
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at 270 to 320 C.
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Philips Semiconductors
Product specification
Digital audio input/output circuit (DAIO)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1315H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 (from 10-10-1995: +31-40-2724825) SCD41 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/05/pp36 Document order number: Date of release: 1995 Jul 17 9397 750 00217

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